In the field of digital electronics, especially in the area of computer electronics, the rate at which commands and data are transferred between devices continues to be driven ever higher. This has lead to the inception of a great number of high speed buses based on a wide variety of differing designs, with some being rather specialized for particular purposes. However, as those skilled in the art will readily recognize, with higher transfer rates comes reduced time periods during which each transfer of addresses, commands and/or data may take place, and as a result, issues with the amount of time required for signals to settle before they can be reliably read, though small, does become increasingly significant.
Various forms of bus termination have become routinely employed as a way to counteract challenging conductor configurations, bus reflections from trace corners and end points, etc. However, the use of bus termination comes at the cost of greater power consumption and/or the provision of higher capacity power sources to provide a termination voltage. With multiple high speed buses being ever more commonly employed in a single electronic device, such as a computer system, the amount of power caused to be consumed by the use of termination can become very large. Also of concern are instances when such consumption of power can become very acute, such as when many or all of the signals of a high-speed bus are simultaneously driven to the same high or low state, and proper preparation for this possibility often requires the use of a termination voltage power source of greater capacity than is desired be allocated to accommodate this effect of using termination.